Testing of integrated circuits (IC's), also called chips or dies, is an important part of the design and manufacture of the circuits. Advantageously,. initial testing is performed while the chips are still held together as parts of a semiconductor slice or wafer. If the chip is faulty, then the design or manufacturing process can be altered to produce the desired results.
The development of higher speed integrated circuits has required the development of new testing techniques. In particular, the use of ordinary wire probes to make connection between the chip and the testing apparatus can no longer be employed because the wire probe inductance produces undesirable large voltage transients as the probe currents change during testing and capacitive and inductive coupling between probe wires generate extraneous signals that confuse the test results. There are essentially six separate functions that should be performed to accurately and reliably test high speed integrated circuits:
1. The probe wires carrying high speed signals should be shielded from one another as much as is practicable to minimize coupling between the probe wires.
2. The probe wires carrying high speed currents should be low inductance to minimize current induced voltage transients.
3. The probe tips should have mechanical compliance to allow each individual probe tip to move independently of the others to assure reliable contacts in the presence of unavoidable small variations in the placement of the probe tips and unavoidable non planarity of the slice or probe mounting during testing.
4. The probe tips that contact the circuit to be tested should be small in size so that chips with closely spaced test pads may be tested.
5. The probe apparatus should be mechanically durable for long lasting reliable operation.
6. The connections between the probe assembly and the testing apparatus should be effected with minimal degradation of the testing signals.
Satisfactory solutions to many of the above requirements that have enjoyed considerable commercial success are disclosed in U.S. Pat. No 4,871,964 issued Oct. 3, 1989 and U.S. Pat. No. 5,373,231 issued on Dec. 14, 1994 and assigned to the same assignee as the present invention. However, when the application requirements are not so stringent, we seek a less expensive structure.
The invention disclosed here describes apparatus that meets the above requirements and is advantageous in that it is simple and inexpensive and it is an extension of a well-developed technology. Possible disadvantages are that the probe assembly may not be as high speed and the probe tips may be less mechanically compliant than the aforementioned solutions. However, for a large number of probe testing applications the new apparatus is expected to be superior due to lower costs and it is expected to be very rugged and allow smaller probe tip separation.
Although this invention is primarily directed toward testing of integrated circuits while still part of a semiconductor line, the apparatus may also be adapted for testing larger structures such as printed circuit boards or ceramic substrates that may include packaged or unpackaged integrated circuit chips.